中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.234199
中文引用格式： 蘇成，夏宏. 一種高效能可重構(gòu)1 024位大數(shù)乘法器的設(shè)計[J]. 電子技術(shù)應(yīng)用，2024，50(3)：31-35.
英文引用格式： Su Cheng，Xia Hong. Design of an efficient and reconfigurable 1 024 bit large numbers multiplier[J]. Application of Electronic Technique，2024，50(3)：31-35.

Design of an efficient and reconfigurable 1 024 bit large numbers multiplier

Abstract： Large number multiplication is often used in algorithms such as SM9 encryption. In order to solve the problem of high delay and energy consumption in key circuits in large number multiplication, a reconfigurable 1 024 bit multiplier based on pipeline was designed. By using 64 bit multiplication units and 128 bit carry ahead addition units, the final result is generated in 20 cycles, alleviating the delay of the addition part in traditional multipliers, achieving circuit multiplexing, and effectively reducing energy consumption. In the SMIC 0.18 μm process library, the critical circuit has a delay of 2.5 ns, a circuit area of 7.03 mm2, and an energy consumption of 576 mW.

Key words : large number multiplication；pipeline；Wallace tree；reconfigurable