中圖分類號(hào)：TP311.5 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.223698 中文引用格式： 徐勁松，嚴(yán)迎建，劉軍偉. 多核專用指令處理器集成開發(fā)環(huán)境設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用，2023，49(8)：93-97. 英文引用格式： Xu Jinsong，Yan Yingjian，Liu Junwei. Design of IDE for multi-core ASIP[J]. Application of Electronic Technique，2023，49(8)：93-97.
Design of IDE for multi-core ASIP
Xu Jinsong，Yan Yingjian，Liu Junwei
(College of Cryptography Engineering， Information Engineering University， Zhengzhou 450004， China)
Abstract： The Integrated Development Environment (IDE) is designed for a multi-core cryptographic instruction coprocessor, including Instruction Set Simulator (ISS), assembler, debugger and other functional modules. It supports software debugging based on assembly language and performance evaluation of cryptographic algorithms. According to the characteristics of the cryptographic algorithm, the simulator of the cryptographic processing engine in the IDE adopts the way of decoding arithmetic instructions in advance to improve the performance of the simulator. On this basis, to meet the requirements of program debugging and algorithm performance evaluation, an instruction level synchronization simulator and a shared data level synchronization simulator are designed using different simulation strategies. The test results show that the speed of the simulation reaches 4.83 MIPS during the algorithm evaluation of the IDE, and the performance evaluation results are consistent with the hardware simulation.
Key words : IDE；ISS；multicore；synchronization
0 引言
處理器的軟件開發(fā)通常需要一個(gè)集成開發(fā)環(huán)境（Integrated Development Environment，IDE），通過集成開發(fā)環(huán)境完成軟件開發(fā)的代碼編程、調(diào)試與優(yōu)化。對(duì)于不同指令集的處理器，通常會(huì)有一個(gè)或多個(gè)軟件開發(fā)環(huán)境，比較知名的集成開發(fā)環(huán)境有桌面處理器的Visual Studio，ARM處理器的ADS、RVDS，單片機(jī)的Keil。對(duì)于專用指令處理器，其指令集通常為某一應(yīng)用領(lǐng)域而設(shè)計(jì)[1-2]，通用處理器需要多條指令才能完成的運(yùn)算，專用指令處理器只需要一條指令就能夠完成，提高了處理器性能，但其指令與其他處理器的指令集不兼容，需要為其提供專用的集成開發(fā)環(huán)境，如TI的CCS。目前有許多科研單位為自己的芯片設(shè)計(jì)了集成開發(fā)環(huán)境[3-4]，為處理器的推廣應(yīng)用提供軟件開發(fā)平臺(tái)。本文設(shè)計(jì)的集成開發(fā)環(huán)境是面向本單位研制的密碼專用指令協(xié)處理器，采用匯編語言編程，能支持單步、執(zhí)行至斷點(diǎn)等常規(guī)調(diào)試方式，支持密碼算法性能評(píng)估。
