ST公司的SPC564A7是 32位Power Architecture MCU,和ST的SPC56xx系列兼容,采用150 MHz e200z4 Power Architecture®內(nèi)核.該系統(tǒng)級芯片(SoC)主要用在中檔引擎控制和汽車傳動控制.本文介紹了SPC564A7主要特性,框圖以及SPC56A-DISP Discovery+開發(fā)板主要特性,電路圖和材料清單.
This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive transmission control applications.
It is compatible with devices in ST’s SPC56xx family and offers performance and capability above that of the SPC563M devices.
The microcontroller’s e200z4 host processor core is built on the Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the STMicroelectronics calibration tool.
SPC564A7主要特性:
■ 150 MHz e200z4 Power Architecture® core
– Variable length instruction encoding (VLE)
– Superscalar architecture with 2 execution units
– Up to 2 integer or floating point instructions per cycle
– Up to 4 multiply and accumulate operations per cycle
■ Memory organization
– 2 MB on-chip flash memory with ECC and read-while-write (RWW)
– 128 KB on-chip SRAM with standby functionality (32 KB) and ECC
– 8 KB instruction cache (with line locking),configurable as 2- or 4-way
– 14 + 3 KB eTPU code and data RAM
– 4 × 4 crossbar switch (XBAR)
– 24-entry MMU
■ Fail Safe Protection
– 16-entry Memory Protection Unit (MPU)
– CRC unit with 3 submodules
– Junction temperature sensor
■ Interrupt
– Configurable interrupt controller (INTC) with non-maskable interrupt (NMI)
– 64-channel eDMA
■ Serial channels
– 3 eSCI modules
– 3 DSPI modules (2 of which support downstream Micro Second Channel [MSC])
– 3 FlexCAN modules with 64 message buffers each
– 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC
■ 1 eMIOS (24 unified channels)
■ 1 eTPU2 (second generation eTPU)
– 32 standard channels
– 1 reaction module (6 channels with 3 outputs per channel)
■ 2 enhanced queued analog-to-digital converters (eQADCs)
– Forty 12-bit input channels
– 688 ns minimum conversion time
■ On-chip CAN/SCI Bootstrap loader with Boot Assist Module (BAM)
■ Nexus: Class 3+ for core; Class 1 for eTPU
■ JTAG (5-pin)
■ Development Trigger Semaphore (DTS)
■ Clock generation
– On-chip 4–40 MHz main oscillator
– On-chip FMPLL (frequency-modulated phase-locked loop)
■ Up to 112 general purpose I/O lines
■ Power reduction modes: slow, stop, and standby
■ Flexible supply scheme
– 5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V , and 1.2 V
■ Designed for LQFP176, LBGA208, PBGA324
圖1. SPC564A7系列方框圖
SPC56A-DISP Discovery+開發(fā)套件
The SPC56A-DISP Discovery+ kit helps to discover SPC56 A line Power Architecture Microcontrollers with full access to CPUs, GPI/O’s and peripherals such as CAN, UART, JTAG, K-Line, LIN at budget price.
Free ready-to-run application firmware examples are available inside SPC5Studio to support quick evaluation and development.
SPC5Studio includes visual configurable code generation engine, board support package (BSP), startup routines, interrupt services, free RTOS (optional) and a full set of low level drivers. SPC5Studio includes HighTec GNU "C" compiler, with a 30-days full free trial license. SPC5Studio is available for free download.
The SPC56A line is designed to address the most complex automotive power train and transmission applications.
The SPC56A key functionality is Time processing units (eTPU) a coprocessor to create events in sync with internal or external signals without flooding the CPU with interrupt to serve.
An E2E Community is available on ST WEB to get ST experts support in getting started quickly with SPC56 microcontrollers
SPC56A-DISP Discovery+開發(fā)套件主要特性:
SPC564A70L7 32-bit 150 MHz e200z4 Power Architecture®core, 2Mbyte on-chip in an LQFP176 package.
Board Supply: Single 5VDC external power supply input.
All GPIOs and DSPI/uSB signals accessible by a 4x36 100mil pin grid array allowing connection of an additional boards for dedicated applications.
JTAG interface (7 x 2 male 100 mil)
2 high speed CAN interface (DB9 male) + 1x extra CAN (2 headers)
2 eSCI interface (DB9 female) or 1
SCI interface + 1 K-LINE interface.
2 deserial serial peripheral interface (DSPI) modules (compatible with Microsecond Bus)
1 Optional high speed Nexus interface
4 LEDs: LE3 for 5 V power on,LE4 for Reset, LE1 and LE2 for GPIO99 and GPIO98 (for user)
12 MHz crystal.
2 potentiometers for ADC quick evaluation
Reset push button.
Board size 145 x 97.5mm
圖2. SPC56A-DISP Discovery+開發(fā)板外形圖
圖3. SPC56A-DISP Discovery+開發(fā)板電路圖
圖4. SPC56A-DISP Discovery+開發(fā)板PCB布局圖
