中圖分類號： TN926；TP393
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.222721
中文引用格式： 王博，王雪迪，時廣軼，等. WiFi-TSN低時延轉換架構[J].電子技術應用，2022，48(4)：24-28，33.
英文引用格式： Wang Bo，Wang Xuedi，Shi Guangyi，et al. WiFi-TSN low latency conversion architecture[J]. Application of Electronic Technique，2022，48(4)：24-28，33.

WiFi-TSN low latency conversion architecture

Abstract： The integration of wireless network and TSN(Time Sensitive Networking) is one of the concerns of industry at present. The traditional gateway based on application layer software has some disadvantages, such as high CPU utilization, long processing delay, poor performance and so on. Therefore, a WiFi TSN low delay conversion architecture is proposed to realize the integration of WiFi network and TSN network. The architecture is implemented in Verilog language, which ensures the predictable delay between communication channels through hardware, and can complete protocol conversion and protocol data forwarding in a very short time. Vivado EDA tool is used to complete the circuit design, and sufficient simulation tests are carried out to evaluate the end-to-end delay performance of the circuit.

Key words : TSN；WiFi；protocol conversion；end-to-end delay