中圖分類號： TN432
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.191337
中文引用格式： 劉穎，田澤，呂俊盛，等. 一種基于Ring-VCO結(jié)構(gòu)的寬頻帶低抖動鎖相環(huán)的設計與實現(xiàn)[J].電子技術應用，2020，46(5)：35-39.
英文引用格式： Liu Ying，Tian Ze，Lv Junsheng，et al. Design and implement of a ring-VCO based PLL with wide frequency range and low jitter[J]. Application of Electronic Technique，2020，46(5)：35-39.

Design and implement of a ring-VCO based PLL with wide frequency range and low jitter

Abstract： A ring-VCO based phase lock loop(PLL) is designed for achieving the wide frequency range and low jitter requirements of high speed communication system. By adjusting the loop bandwidth which is closely related to the lock-in frequency it reduces the loop noise and accelerates loop locking. Adopting the comparator in reference circuit to compare the locking control voltage with the reference voltage to flexibly change the current in other module, and adjusting the loop parameters according to different lock-in frequencies, the lock-in time is greatly reduced. At the same time, the differential symmetrical structure of the four-stage differential ring oscillator and duty cycle adjusting circuit is used to reduce the circuit noise. This chip is fabricated in 40 nm CMOS process, the measured results show that the output frequency is from 1.062 5 GHz to 5 GHz, the performance of the signal at 5 GHz is good and jitter is 39.6 ps.

Key words : phase lock loop；ring oscillator；wide frequency range；low jitter