NS 公司的LMK04800系列是雙回路PLL的低噪音時(shí)鐘抖動(dòng)清理器，具有超低的RMS抖動(dòng)性能：12 kHz -20 MHz為111fs RMS，100 Hz - 20 MHz為123fs RMS，工作電壓3.15 V 到 3.45 V，時(shí)鐘速率高達(dá)1536 MHz，可以滿足新一代系統(tǒng)所需的要求，主要用在數(shù)據(jù)轉(zhuǎn)換器時(shí)鐘/無(wú)線基礎(chǔ)設(shè)備，網(wǎng)絡(luò)， SONET/SDH, DSLAM，醫(yī)療/視頻/軍用/航天以及測(cè)試測(cè)量設(shè)備。本文介紹了LMK04800主要特性，詳細(xì)方框圖和多種模式下的功能方框圖以及典型應(yīng)用電路。
LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
The LMK04800 family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum ™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation.
PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior closein phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
LMK04800主要特性：
■ Ultra-Low RMS Jitter Performance
— 111 fs RMS jitter (12 kHz to 20 MHz)
— 123 fs RMS jitter (100 Hz to 20 MHz)
■ Dual Loop PLLatinum PLL Architecture
— PLL1
■ Integrated Low-Noise Crystal Oscillator Circuit
■ Holdover mode when input clocks are lost
— Automatic or manual triggering/recovery
— PLL2
■ Normalized [1 Hz] PLL noise floor of -227 dBc/Hz
■ Phase detector rate up to 155 MHz
■ OSCin frequency-doubler
■ Integrated Low-Noise VCO
■ 2 redundant input clocks with LOS
— Automatic and manual switch-over modes
■ 50% duty cycle output divides, 1 to 1045 (even and odd)
■ LVPECL, LVDS, or LVCMOS programmable outputs
■ Precision digital delay, fixed or dynamically adjustable
■ 25 ps step analog delay control.
■ 14 differential outputs. Up to 26 single ended.
— Up to 6 VCXO/Crystal buffered outputs
■ Clock rates of up to 1536 MHz
■ 0-delay mode
■ Three default clock outputs at power up
■ Multi-mode: Dual PLL, single PLL, and clock distribution
■ Industrial Temperature Range: -40 to 85 ℃
■ 3.15 V to 3.45 V operation
■ Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)
LMK04800目標(biāo)應(yīng)用：
■ Data Converter Clocking / Wireless Infrastructure
■ Networking, SONET/SDH, DSLAM
■ Medical / Video / Military / Aerospace
■ Test and Measurement
圖1。LMK0480x詳細(xì)方框圖
圖2。雙回路模式的LMK0480x簡(jiǎn)化方框圖
圖3。單回路模式的LMK0480x簡(jiǎn)化功能方框圖
圖4。零延遲單回路模式的LMK0480x簡(jiǎn)化功能方框圖
圖5。模式時(shí)鐘分布LMK0480x簡(jiǎn)化功能方框圖
圖6。LMK0480x應(yīng)用電路圖
詳情請(qǐng)見(jiàn)：
http://www.national.com/ds/LM/LMK04800.pdf
